1. Field of the Invention
The present invention relates to a semiconductor device utilized for electric power and, in particular, a static induction transistor which is rendered normally OFF under high application voltage and has a normally OFF function suitable for high withstand voltage and high-speed switching operation.
2. Description of the Related Art
Conventionally, those semiconductor devices utilized for electric power, etc., demand low ON voltage low ON resistance, high speed and high withstand voltage functions so as to achieve high performance.
As an ordinary semiconductor element for electric power, etc., a bipolar mode static induction transistor (hereinafter referred to as a BSIT) is known which operates a unipolar-structured static induction transistor (hereinafter referred to as an SIT) in bipolar mode.
The basic BSIT structure will now be explained below, for example, with reference to FIG. 7. Here an N-channel type will be explained below by way of example.
In BSIT, a high resistance, n.sup.- type low concentration impurity layer 2 is formed on one major surface of an n.sup.+ type silicon substrate 1 and electrically isolated p.sup.+ type gates 3a, 3b and n.sup.+ type source 4 are formed over the low concentration impurity layer 2. An n.sup.- type channel region 5 is formed beneath the source 4 at an area surrounded with the gates 3a, 3b. A gate(3a)-to-gate(3b) area is called a channel width. Thermal oxide films 6 are provided over the silicon substrate 1 and a gate electrode 7 and source electrodes 8 are formed relative to the thermal oxide films 6. A drain electrode 9 is formed on the other major surface side of the silicon substrate 1.
Here, the OFF state (blocked state) of BSIT shows, like an ordinary MOSFET, an OFF state set by a blocking voltage (withstand voltage) determined by averianche breakdown in a pn junction and an OFF state set by a blocked voltage (withstand voltage) defined by a leak current flowing across a source-to-drain circuit at a gate voltage=0 V (at a zero gate voltage time).
In order to utilize BSIT (FIG. 7) in normally OFF state a depletion layer is made a completely pinchoff state in the channel region 5 with the channel width narrowed, for example, on the order of 2 .mu.m and, by so doing, a potential barrier is created relative to electrons in the source 4. That is, BSIT is so configured that it has no such pn junction structure as to make a current path in a normally OFF state but that it is maintained in an OFF stage by a potential barrier. The potential barrier is governed principally by the channel width, gate depth, gate impurity concentration and channel impurity concentration and largely governed by not only these parameters but also the drain voltage applied.
In this structure, the potential barrier is adequately high in the case where the drain voltage is set relatively low and, therefore, there is less probability that source electrons will thermally be moved beyond the potential barrier. When, a however, a drain voltage as high as a few hundreds of volts is applied to BSIT, the potential barrier level is decreased, thus increasing a probability that the source electrons will thermally be moved beyond the potential barrier. Such a high drain voltage leads to an increased leak current, thus failing to maintain BSIT in a normally OFF state.
FIG. 8 shows an improved version of BSIT, as a second conventional structure, having a pn junction structure in a channel region where, for example, p.sup.+ type, relatively low concentration impurity layers are provided in an n type channel region. This BSIT structure raises the potential barrier level and hence decreases a leak current involved. Here it is to be noted that, in FIG. 8, the same reference numerals are employed to designate portions or elements corresponding to those shown in FIG. 7 and no further explanation is, therefore, omitted.
This BSIT structure has a p type channel region 10 on an n.sup.- type channel region 5 of the first conventional BSIT structure. The withstand voltage of such BSIT is deter mined by the specification of the channel region as well as the impurity concentration and thickness of the n.sup.- type low concentration impurity layer 2.
In the second BSIT structure, if a drain voltage applied is, for example, 600 V, it is only necessary to provide a channel width 2 .mu.m and channel region depth 3 .mu.m at a surface concentration 5.times.10.sup.15 cm.sup.-3 of the p type impurity layer.
In the case where the aforementioned impurity concentration layer 10 has an adequately low concentration level so that complete depletion is achieved in the channel region at a turn-off time upon switching, no carriers exist in the channel region, thus ensuring the same high-speed switching characteristic as that of the basic first BSIT structure.
As a third conventional device an insulated gate field effect transistor is known which can perform conductivity modulation as disclosed in Published Unexamined Japanese Patent Application 4-76498.
In the insulated gate field effect transistor shown in FIG. 9, an n type high resistive layer 2a is formed on a p type drain region 9a and a projected area is provided on that semiconductor substrate portion forming the n type high resistive layer 2a. n.sup.+ type source regions are provided on the upper source portions of the projected area such that surrounding gate oxide film and polysilicon gate electrode 7 are formed on that projected area. A p type grid area 4a is provided on the base portion of the projected area belonging to the n type high resistive layer 2a. Further source electrodes are so formed as to be placed at the same potential as those of the n type source region 4 and p type grid areas 4a.
In the insulated gate field effect transistor shown in FIG. 9, when, in the ON state, a voltage exceeding a threshold voltage is applied to the gate electrode, a channel layer is formed at an interface between the gate insulating film and a semiconductor channel formation area. As a result, the injection of majority carriers from the source region and injection of minority carriers from the p.sup.+ drain region simultaneously occur in the n type high resistive layer 2a, enabling a high current to flow due to the n type high resistive layer 2a being conductivity modulated.
Further, the p type grid area draws a greater portion of the minority carriers which is injected from the p.sup.+ drain region into the grid region. It is thus possible to prevent occurrence of a latch-up at a parasitic thyristor present in the insulated gate field effect transistor and also to draw those minority carriers at the OFF state.
The aforementioned conventional semiconductor device presents the following problems.
In actual practice, a drain voltage as high as a few hundreds of volts is applied to the first and second semiconductor devices (BSIT). It is, therefore, necessary to completely block a leak current and to achieve a normally OFF state. For this reason it is necessary to enhance the impurity concentration cf the impurity layer 10 opposite in conductivity type to the channel region or to narrow the channel width.
When the impurity layer 10 of the opposite conductivity type has its impurity concentration enhanced, no complete depletion occurs in the channel region. Since a higher resistance is involved in the channel region than the gate region 3, high-speed switching operation is solved down, at the turn-off time upon switching, due to the built-up effect of minor carriers present beneath the impurity layer 10 of the conductivity type opposite to that of the channel region. Further, when the impurity density of the impurity layer 10 is raised the channel region has its characteristic approach the bipolar transistor, thus causing a drop of h.sub.FS.
Further, the narrowing of the channel width leads to the narrowing of the current path of electrons in the source region 4 which provides a main portion of the drain current. This also causes a drop in ON resistance and in h.sub.FS.
Although, in the insulated gate yield effect transistor as set out in connection with the third conventional device, the drawing of the minority carriers and high-speed switching are achieved so that latch-up is prevented, since the insulated gate field effect transistor creates a pn junction between the p.sup.+ drain region and the n type high resistive layer, no drain current flows until the drain voltage reaches a forward bias voltage (.about.0.7 V for Si). That is, it is not possible to achieve a low ON voltage.
Further, the insulated gate field effect transistor cannot prevent latch-up completely from a structural viewpoint due to the presence of the parasitic thyristor.
In the insulated gate field effect transistor, those minority carriers injected from the drain are ejected via the grid region. However, the grid region is placed at the same potential as that of the source region and it is, therefore, not possible to achieve an adequately high-speed switching operation due to a relatively large build-up effect of the minority effect injected from the drain.